module S1(clk,
	  rst,
	  updown,
	  S1_done,
	  RB1_RW,
	  RB1_A,
	  RB1_D,
	  RB1_Q,
	  sen,
	  sd);

  input clk,
        rst,
        updown;

  output S1_done,
         RB1_RW;
  
  output [4:0] RB1_A;
  
  output [7:0] RB1_D;
  
  input [7:0] RB1_Q;
  
  inout sen,
        sd;

reg S1_done;
reg RB1_RW;
reg [4:0] RB1_A;
reg [7:0] RB1_D;

reg sd_temp_s1;
reg sen_temp_s1;
reg [4:0]count_init;
reg [4:0] en_21;
reg [7:0] RQ_temp [17:0];
reg [4:0] count_X;
reg [2:0] count_Y;
reg [3:0]count_rb2;
reg en_X;
/*
wire [7:0]  RQ_t_00;
wire [7:0]  RQ_t_01;
wire [7:0]  RQ_t_02;
wire [7:0]  RQ_t_03;
wire [7:0]  RQ_t_04;
wire [7:0]  RQ_t_05;
wire [7:0]  RQ_t_06;
wire [7:0]  RQ_t_07;
wire [7:0]  RQ_t_08;
wire [7:0]  RQ_t_09;
wire [7:0]  RQ_t_10;
wire [7:0]  RQ_t_11;
wire [7:0]  RQ_t_12;
wire [7:0]  RQ_t_13;
wire [7:0]  RQ_t_14;
wire [7:0]  RQ_t_15;
wire [7:0]  RQ_t_16;
wire [7:0]  RQ_t_17;

assign RQ_t_00 = RQ_temp[ 0];
assign RQ_t_01 = RQ_temp[ 1];
assign RQ_t_02 = RQ_temp[ 2];
assign RQ_t_03 = RQ_temp[ 3];
assign RQ_t_04 = RQ_temp[ 4];
assign RQ_t_05 = RQ_temp[ 5];
assign RQ_t_06 = RQ_temp[ 6];
assign RQ_t_07 = RQ_temp[ 7];
assign RQ_t_08 = RQ_temp[ 8];
assign RQ_t_09 = RQ_temp[ 9];
assign RQ_t_10 = RQ_temp[10];
assign RQ_t_11 = RQ_temp[11];
assign RQ_t_12 = RQ_temp[12];
assign RQ_t_13 = RQ_temp[13];
assign RQ_t_14 = RQ_temp[14];
assign RQ_t_15 = RQ_temp[15];
assign RQ_t_16 = RQ_temp[16];
assign RQ_t_17 = RQ_temp[17];
*/

assign sd = (~updown)?sd_temp_s1:1'bz;
assign sen = (~updown)?sen_temp_s1:1'bz;

//RQ_temp
//always@(negedge clk or posedge rst)
always@(negedge clk)
  begin
    RQ_temp[RB1_A] <= RB1_Q;
  end

//count_array_X 
always@(negedge clk or posedge rst)
  begin
    if(rst)
      count_X <= 21;
    else if (count_X == 0)
      count_X <=  21;
    //else if (count_init > 18 )
    else if (en_X)
      count_X <= count_X - 1'b1;
  end
//count_array_Y 
always@(negedge clk or posedge rst)
  begin
    if(rst)
      count_Y <= 7;
    else if (count_Y == 0)
      count_Y <= 0;
    else if (count_X == 0)
      count_Y <= count_Y - 1'b1;
  end
//en_X
always@(negedge clk or posedge rst)
  begin
    if(rst)
      en_X <= 0;
    else if (count_init > 17 )
      en_X <= 1;
  end



//count_init
always@(posedge clk or posedge rst)
  begin
    if(rst)
      count_init <= 0;
    else if (count_init == 19)
      count_init <= 0;
    else 
      count_init <= count_init + 1'b1;
  end

//s1_done
always@(posedge clk or posedge rst)
  begin
    if(rst)
      S1_done <= 0;
    else if (RB1_A==17 && ~RB1_RW ) 
      S1_done <= 1; 
  end
//rb1_rw
always@(negedge clk or posedge rst)
  begin
    if(rst)
      RB1_RW <= 1;
    else if(sen && updown)
      RB1_RW <= 0;
    else
      RB1_RW <= 1;
  end

//en_21
always@(negedge clk or posedge rst)
  begin
    if(rst)
      en_21 <= 0;
    else if (count_init== 19 && en_21==0)
      en_21 <= 1;
    else if (en_21 == 22)
      en_21 <= 1;
    else if (en_21 > 0) 
      en_21 <= en_21 + 1'b1;
  end




  
//sen_temp_s1
always@(negedge clk or posedge rst)
  begin
    if(rst)
      sen_temp_s1 <= 1;
    else if (en_21 == 22)
      sen_temp_s1 <= 1;
    //else if (count_init>18 && en_21 == 1)
    else if (en_X && en_21 == 1)
      sen_temp_s1 <= 0;
  end


//sd_temp_s1
always@(negedge clk or posedge rst)
  begin
    if(rst)
      sd_temp_s1 <= 0 ;
    else if (count_X < 18 ) 
      sd_temp_s1 <= RQ_temp[count_X][count_Y];
    else if(count_Y==7) begin
      if (count_X ==20 ||count_X ==19 ||count_X ==18)
        sd_temp_s1 <= 0;
    end
    else if(count_Y==6)begin
      if (count_X ==20 )
        sd_temp_s1 <= 0;
      else if (count_X == 19)
        sd_temp_s1 <= 0;
      else if (count_X == 18)
        sd_temp_s1 <= 1;
    end
    else if(count_Y==5)begin
      if (count_X ==20 )
        sd_temp_s1 <= 0;
      else if (count_X == 19)
        sd_temp_s1 <= 1;
      else if (count_X == 18)
        sd_temp_s1 <= 0;
    end
    else if(count_Y==4)begin
      if (count_X ==20 )
        sd_temp_s1 <= 0;
      else if (count_X == 19)
        sd_temp_s1 <= 1;
      else if (count_X == 18)
        sd_temp_s1 <= 1;
    end
    else if(count_Y==3)begin
      if (count_X ==20 )
        sd_temp_s1 <= 1;
      else if (count_X == 19)
        sd_temp_s1 <= 0;
      else if (count_X == 18)
        sd_temp_s1 <= 0;
    end
    else if(count_Y==2)begin
      if (count_X ==20 )
        sd_temp_s1 <= 1;
      else if (count_X == 19)
        sd_temp_s1 <= 0;
      else if (count_X == 18)
        sd_temp_s1 <= 1;
    end
    else if(count_Y==1)begin
      if (count_X ==20 )
        sd_temp_s1 <= 1;
      else if (count_X == 19)
        sd_temp_s1 <= 1;
      else if (count_X == 18)
        sd_temp_s1 <= 0;
    end
    else if(count_Y==0)begin
      if (count_X ==20 )
        sd_temp_s1 <= 1;
      else if (count_X == 19)
        sd_temp_s1 <= 1;
      else if (count_X == 18)
        sd_temp_s1 <= 1;
    end
  end


//count_rb2
always@(posedge clk or posedge rst)
  begin
    if(rst)
      count_rb2 <= 0;
    else if (count_rb2==13)
      count_rb2 <= 0;
    else if (updown && ~sen) 
      count_rb2 <= count_rb2+ 1'b1;
  end

//RB1_A
always@(negedge clk or posedge rst)
  begin
    if(rst)
      RB1_A <= 0;
    else if(RB1_A == 17 && ~updown)
      RB1_A <= RB1_A;
    else if (~updown)
      RB1_A <= RB1_A + 1'b1;
    else if (updown && count_rb2 < 5)
      RB1_A[4-count_rb2] <= sd;
      
  end



//RB1_D
always@(negedge clk or posedge rst)
  begin
    if(rst)
      RB1_D <= 0;
    else if (count_rb2 > 4)
      RB1_D[12-count_rb2] <= sd;
  end


endmodule
